ADT7518
Rev. A | Page 18 of 40
The ADT7518 powers up with averaging on. This means every
channel is measured 16 times and internally averaged to reduce
noise. The conversion time can also be sped up by turning off
the averaging. This is done by setting Bit C5 of the Control
Configuration 2 register (Address 19h) to 1.
FUNCTION DESCRIPTIONVOLTAGE OUTPUT
Digital-to-Analog Converters
The ADT7518 has four resistor string DACs fabricated on a
CMOS process with resolutions of 12, 10, and 8 bits, respec-
tively. They contain four output buffer amplifiers and are
written to via I
2
C serial interface or SPI serial interface. See
the Serial Interface section for more information.
The ADT7518 operates from a single supply of 2.7 V to 5.5 V,
and the output buffer amplifiers provide rail-to-rail output
swing with a slew rate of 0.7 V/祍. All four DACs share a com-
mon reference input, VREF-IN. The reference input is buffered to
draw virtually no current from the reference source because it
offers the source a high impedance input. The devices have a
power-down mode in which all DACs may be turned off
completely with a high impedance output.
Each DAC output will not be updated until it receives the
LDAC command. Therefore, while the DAC registers would
have been written to with a new value, this value will not be
represented by a voltage output until the DACs have received
the LDAC command. Reading back from any DAC register
prior to issuing an LDAC command will result in the digital
value that corresponds to the DAC output voltage. Thus, the
digital value written to the DAC register cannot be read back
until after the LDAC command has been initiated. This LDAC
command can be given by either pulling the LDAC
pin low
(falling edge loads DACs), setting up Bits D4 and D5 of the
DAC configuration register (Address 1Bh), or using the LDAC
register (Address 1Ch).
When using the LDAC
pin to control the DAC register loading,
the low going pulse width should be 20 ns minimum. The
LDAC
pin has to go high and low again before the DAC
registers can be reloaded.
Digital-to-Analog Section
The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the VREF-IN pin or the on-chip reference of 2.25 V provides
the reference voltage for the corresponding DAC. Figure 38
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
N
REF
OUT
D
V
V
2
?/DIV>
=
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0 to 255 for ADT7518 (8 bits)
N = DAC resolution
Resistor String
The resistor string section is shown in Figure 39. It is simply a
string of resistors, each of approximately 603 &. The digital
code loaded to the DAC register determines at which node on
the string the voltage is tapped off to be fed into the output
amplifier. The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Because it is a
string of resistors, it is guaranteed monotonic.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
OUT
-A
OUTPUT BUFFER
AMPLIFIER
GAIN MODE
(GAIN = 1 OR 2)
REFERENCE
BUFFER
INT V
REF
V
REF
-IN
Figure 38. Single DAC Channel Architecture
R
R
R
R
R
TO OUTPUT
AMPLIFIER
Figure 39. Resistor String
STRING
DAC A
2.25V
INTERNAL V
REF
V
REF
-IN
STRING
DAC B
STRING
DAC C
STRING
DAC D
Figure 40. DAC Reference Buffer Circuit
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